Texas Instruments: Progress on Next-Gen Cu Pillars

While flip chip technologies are becoming more and more mainstream, traditional solder or Cu Pillar interconnect pitches used in both low and high end applications face technical limitations as device scaling requirements push flip chip pad density limits. At ECTC 2011, Mark Gerber, Manager of CU and TSV interconnect at TI presented the company's work developing fine-pitch Cu pillar technologies to enable next-generation silicon nodes. Chip Scale Review spoke with Mark about the advantages and challenges of this technology.

CSR: What limitations are traditional flip chip technologies experiencing due to device scaling?

Gerber: For current pitches of 150 to 200µm, solder flip chip bumps are the most commonly used technology today. However, the ability to create solder interconnects at pitches below these values have a number of process and design related challenges. One of the technical limitations for driving traditional solder flip chip below the 150um pitch is the ability to plate or drop solder balls that create the solder bump on the die. In addition, the die to substrate standoff height is determined by the flip chip bump collapse height and adequate space between the die and substrate are critical in ensuring full die under fill coverage. On the design consideration, larger solder flip chip bumps consume a larger area of the top substrate surface area which will limit the routing flexibility and raw design layout area. This can force designs into a higher number of substrate layers which generally is not preferred.

CSR: Can you describe briefly describe this next-generation technology.

Gerber: Fine Pitch Cu Pillar technology is an advancement in both bumping and assembly process technologies that allows improved flexibility in both silicon and package design. The two key components of the Cu Pillar technology are the bumping process- the creation of Copper Pillars, and the assembly process- how to integrate the Cu Pillar bumped die into a package. The Copper Pillars are plated on the wafer with traditional plating technology to form the copper pillar and the lead-free solder cap. For assembly, there are two main methods for assembling the die to substrate-mass reflow and thermo compression bonding. These process options are described in detail in the ECTC 2011 paper and can be referenced for the differences.

Figure 2: Fine Pitch Cu Pillar bumps.

CSR: How do fine-pitch Cu Pillar technologies address the limitations of traditional flip chip bumping?

Gerber: Die to substrate standoff height, bumping pitch and substrate design layout are several challenging areas that fine pitch flip chip is targeted to address. As mentioned previously, Fine-pitch Cu Pillar takes up a smaller cross sectional area on both the die and substrate for interconnect, making it more flexible for routing, and allows designers more room for routing substrate trace lines out of the package.

CSR: What features about this technology are particularly unique, and what are the pros and cons?

Gerber: Cu pillar has been in market for a number of years for pitches ranging from 200um - 180 µm. What's unique to fine-pitch Cu Pillar is its scaleability throughout the whole range of pitches from 200µm down to 40µm. The developed bump and assembly processes are what allow for this scalability at lower pitches, which in turn enables higher density designs. Electromigration data has also shown to be very positive across various Cu Pillar interconnect structures, which also will become more important especially as die bond pad pitches are driven down and the cross sectional area of the joint is reduced. Regarding future challenges, there are some equipment infrastructure gaps and it will take some time for industry to close these gaps.

CSR: How does this compare to similar technologies?

Gerber: The lead competing technology is fine-pitch gold stud flip chip, which has been used in Asia for quite a few years (Figure 2). It's been fairly successful, and is built on wire bond technology, forming a gold stud on a pad. Limitations here center on its ability to migrate to next gen silicon node. Gold stud wire based process is harsher on the bond pads, and scalability can be a challenge. These limitations can be controlled with copper pillar. You can change height to whatever you want rather than being limited to the kind of stud you can form.

Figure 2a: Gold stud bonding. Figure 2b: Fine pitch Cu Pillar bump.

CSR: What are the main application drivers for this next-gen fine pitch technology?

Gerber: Devices with high I/O to die size ratios and devices with challenging substrate routing requirements may be good candidates.

CSR: What are will be important milestones for the future of this technology?

Gerber: Cu Pillar is gaining momentum in the industry and one milestone for the evolution of this technology may be how it is integrated with future technologies such as through silicon via (TSV).

Mark Gerber is a Senior Member of the Technical Staff at TI and is currently managing TI's Worldwide Cu Pillar Package Engineering team and has responsibility for the overall development and introduction of new devices in this technology. Mark has worked in the Semiconductor Packaging field for over 17 years and focused on key areas such as Stacked Die, Package on Package, TSV and Fine Pitch Flip Chip. Mark has published a number of papers and has 24 issued patents.