The International Magazine for Device and Wafer-Level Test, Assembly, and Packaging Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS, MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century
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CSR Tech Monthly

What’s New in Inspection Tools and Technologies

Inspection tools are critical to the whole packaging supply chain, especially with the latest interconnect technologies for advanced packaging including 3D stacking. It seems like all the manufacturers tools for various inspection technologies including metrology, X-ray, automated optical inspection, scanning acoustic microscopy, and scanning electron microscopy, are turning out new products or enhancements to existing once to suit the next-generation packages.

At SEMICON West in July, Nordson DAGE showcased its XD7600NT Diamond X-ray inspection system equipped with the company’s unique sealed transmissive X-ray tube, that achieves 0.1µm feature recognition and up to 10 watts of power, together with the 3 mega pixel long lifetime CMOS flat panel detector. The company also showed its µCT 3D modeling and volumetric measurement capability suited to analytical investigation of critical applications such as stacked die, MEMS, PiP, and PoP devices.

This year’s technology update from Rudolph Technologies begins with the introduction of The NSX®320 Automated Macro Inspection System, designed specifically for advanced packaging processes that use through silicon vias (TSV) to connect multiple die in a single package. The system also provides critical inspection capabilities for edge trimming metrology, wafer alignment during bonding processes, sawn wafers on film frames and other TSV related processes.  Second is the introduction of an improved yield enhancement system, based on the Yield Dynamics software technology it acquired from MKS Instruments last year. Genesis® Enterprise version is an offline yield analysis and data mining software with parametric yield management tools designed to maximize factory efficiency and identify causes of yield loss. Enhancements that building on the previous version include more robust genealogy, more efficient charting and analysis, easier data management and more intuitive wafer/sheet mapping and bin maps.

Olympus Integrated Technologies America, Inc. (Olympus-ITA), introduced the latest 3DIR Metrology and Defect Review System at SEMICON West 2011. The system uses a confocal IR laser scanning microscopy technology for measuring post bond parameters of three dimensional stacked integrated circuits (3DS-ICs).  This non-destructive, through-silicon metrology technique monitors a variety of post bond parameters including overlay alignment accuracy, bonding interface thickness variations, and bonding interface quality including pre- and post-bond defect inspection and review.

As part of its laundry list of recent accomplishments, EV Group has integrated an inline metrology module into EVG’s temporary bonding system to optimize wafer bonding and thinning processes, ultimately maximizing yield and investments.  By using an infrared beam, carrier thickness and uniformity is measured. Additionally, bonding voids and other imperfections in the stack can be detected. From there, it can be determined whether the bonded pair is ready for backgrinding, or if it needs to go through re-work before by debonding and bonding the wafer again.

Sonoscan’s latest offering is a high-end lab acoustic micro imaging system, the Gen6™ C-SAM®, which incorporates new and upgraded capabilities building on its predecessor, the Gen5™. While the Gen6 maintains the same look as the Gen5, the electronics and operating system are on a completely redesigned platform. New features are intended for analyzing more complex problems as for example, samples built with 3D packaging technology.  Software enhancements allow for automatic and simultaneous imaging of a sample at up to 200 different gates (horizontal “slices”), which is very useful when searching for subtle changes in a sample such as “white bumps”, die tilt, stacked die defects, etc.

These represent some of the most recent offerings in the market place.  Look for more in upcoming issues of Chip Scale Review Magazine.

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