EV Group: Progress on Advanced C2W Bonding
When it comes to 3D chip stacking, chip-to-wafer (C2W) processes have proven to be the way to go for stacking known-good-die (KGD) for best yields, or if the dies being stacked are of different size.
Unfortunately, sequential C2W processes have historically been time consuming, achieving low throughput; making it a costly approach. Several approaches are under development to address this; all involving a two-step die placement followed by collective permanent bond. Chip Scale Review recently spoke with Thorsten Matthias, Business Development Director for EV Group, to learn more about the company's collaboration with Datacon to develop what they've dubbed Advanced Chip to Wafer (C2W) Bonding.
CSR: What was the initial motivation to develop this two-step approach for advanced C2W bonding? What are the advantages to the two-step, advanced chip to wafer bonding process that EVG and Datacon are developing?
Matthias: The dies being stacked for C2W stacking already have bond pads and TSVs in the die, so when you stack them, you need to achieve both a mechanical bond and electrical interconnect, which requires a metal bond. While a reflow bond is sufficient for low I/O, higher density (which means smaller microbumps) really requires Cu-Sn or Cu-Cu bonding to get a reliable joint. Because Cu-Cu bonding is driven by metal ion diffusion, it is a slow process, proportionate to the temperature. It involves heating up the die stack to create mechanical and electrical contact. If you do this in a serial manner, each die must be heated up to 200°C for a length of time then be cooled down. Additionally, the process must be done in inert atmosphere to avoid corrosion or oxidation of the pads or contacts. Also, when you're working with CuSn and thin die, it's difficult to place the die on the wafer and reflow it. Die warpage must be controlled during bonding by application of pressure to maintain flatness and assure all the I/Os are connecting. The advantage of splitting the process into two parts is that the wafer can be fully populated by first tacking the die in place temporarily, and then be transferred to a dedicated bond chamber where the permanent bond is done all at once (Figure 1).
Figure 1. Advanced chip-to-wafer (AC2W) bonding
CSR: As we understand it, there was also an issue of speed and accuracy in the chip placement step for C2W bonding. Is there a system now available that combines both the speed and accuracy needed to achieve cost-effective throughputs for high volume manufacturing?
Matthias: In the past, there were die bonders that could achieve high accuracy, but at low throughput. The tools that could achieve the required throughput didn't have the required accuracy. This problem has now been solved. Datacon has systems that can provide high speed and high accuracy placement to achieve higher throughput of chip to wafer bonding. The throughput is particularly significant when dealing with small die that are placed in high numbers-for example, a couple thousand die per hour. Every second you add to the cycle time adds to the total stacking time.
However the real issue is still the permanent bond step. When performed sequentially, it can take 4-5 hours per wafer just for the permanent bond. If you place all the dies first, then transfer the populated wafer to the bond chamber, all the dies can be bonded in half an hour. This is a significant economic advantage.
CSR: Are wafers put through both the tacking and permanent bonding step one at a time, or can the permanent bond be done in a batch process to speed it up further?
Matthias: Typically you would only use one wafer at a time. One challenge with C2W is that the dies being placed on the wafer might come from different wafers and have thickness variation. Overcoming this problem requires compliance in applying the pressure in order to compensate for thickness variation. There are some interesting concepts being developed with placing multiple dies and bonding the whole stack at once. This would be the "Holy Grail" but there are technical issues, for example, how to keep the die in place and avoid any shift in stack.
There are some studies being done to see if the Cu-Cu bonding can be split into two steps, with the mechanical bond established first followed by a batch annealing process to achieve the electrical contact.
CSR: Has a suitable tacking method been developed to keep the dies in place while transferring the populated wafer from pick-and-place equipment to the final bond equipment?
Matthias: Several methods have been developed to accomplish this. First, a temporary tacking material is applied to keep the die in place. During the bonding process, it evaporates. Depending on the material and process used, an underfill step may be required after bonding or sealing rings are placed around the die, in which case no underfill is necessary. Alternatively a dielectric like BCB can be used by spin coating it on the wafer side, followed by a photolithography process. BCB provides a bit of tackiness, and during the bonding process it reflows and fills in the gaps around the contacts, simultaneously creating a dielectric layer and underfill. Flux dipping is also an option for a tacking step. Another option is to use anisotropic conductor films (ACF) which is applied prior to singulation as part of the debonding step, where a stack of dicing tape-ACF-thin wafer is created. In this case, when you place the die, the tacking material is already there. It's an elegant process. Gas entrapment is avoided by applying vacuum during the ACF lamination process.
CSR: Are there any situations where one tacking method/material is better suited than others?
Matthias: At this point in time we see interest in the market for all these approaches and support all of them. There may come a time where one or two shakes out to be a better option.
CSR: When do you anticipate that the Advanced Chip to Wafer process will be ready for commercialization?
Matthias: From the equipment readiness perspective, we have pick and place systems that have high accuracy and high speed, as well as the bonding equipment available. The Advanced Chip to Wafer process was qualified for production by a major European IDM in 2005. However, the whole TSV infrastructure had to be developed first before this technology could take off. During the past few years we have been working very actively on the integration of thin TSV wafer manufacturing and subsequent Advanced Chip to Wafer bonding. Several of our customers are currently fine-tuning and qualifying the process. We expect to see high volume manufacturing next year, 2012.