STATS ChipPAC - Bumping Right Along

Wafer bumping is big business at STATS ChipPAC, serving as a vital part of the company's flip chip package business, as well as its wafer-level-chip-scale-package (WLCSP) and embedded Wafer Level Ball Grid Array (eWLB) business. To accommodate the growing demand, STATS ChipPAC has wafer bumping operations in Singapore, Taiwan and China; each specific to the products being manufactured at those locations. Since September, the company has announced facility expansions to 300mm in both the Singapore and Taiwan locations. Chip Scale Review spoke with Dr. Raj Pendse, VP of Product & Technology Marketing at STATS ChipPAC, to learn more about the company's wafer bumping services and plans for future growth.

CSR: What wafer bumping services does STATS ChipPAC currently offer its customers?

Pendse: At STATS ChipPAC, we view wafer bumping in two ways. We're in the flip chip package business, which requires bumped die in the package. Secondly, as part of our wafer-level-chip-scale-package (WLCSP) business, we ship bumped die. Which bumping technology is used depends on different things; the alloy composition, bump pitch, I/O, and end-product. We offer plating, printing, and ball drop processes using various alloys.

CSR: Can you explain the differences of each of your bumping operations, and the strategies behind these decisions?

Pendse: The latest activity is our recently expanded 300mm facility in Taiwan. We've chosen this location due to our relationship with the leading foundries.  The closer we are to the foundry, the easier it is to leverage that. Taiwan is where we do wafer level bumping for fine pitch flip chip packages using plated bump technology.  We do traditional Sn-Pb (eutectic and high lead) bumps today, but are transitioning into lead free solder and our proprietary copper column bump with Pb free solder cap to support the increasing demand for lead free and green packaging.

Our bumping operation in Singapore serves the wafer level CSP (WLCSP) market as well as bumping for eWLB and Through Silicon Via (TSV) technologies (Figure 1).  Currently, we use a printed bump technology in Singapore, which is more suited for WLCSP products. The benefit  is being able to produce any alloy composition with printing, but the technology is somewhat limited with regards to scaling pitch.

Figure 1. 200mm bumping facility in Singapore.

The third bumping location is our 200mm facility in China. We continue to expand packaging in China, which includes flip chip and wafer bumping. Since the foundries in that area primarily serve analog and RF products which are produced on 200 mm wafers, it makes sense to maintain the 200mm facility there. Similar to our operation in Taiwan, the bump technologies we do there are plated copper column and lead-free.

CSR: What decides which wafer bumping method is used? Is there a trend away from ‘traditional' bumping processes to more advanced approaches?

Pendse: How fine-pitch the bump needs to be can determine the technology used. Plating is much more scalable, and can achieve pitches ranging from 200 um down to 40µm for  “microbumps” which are used in 3D TSVs. Printed bumping is proven down to 150 um pitch  and allows the use of any alloy composition that provides the best mechanical properties. A limitation of printed bumps is that the printing process always creates some level of voiding. When applications are sensitive to the presence of voids, it's better to go with plating processes (Figure 2).

Figure 2. SEM of plated bumps on a wafer.

There is also an industry trend towards higher I/O density with applications going to as high as 20-50 I/O per mm2. It's hard to achieve this I/O density with solder because of the “stubby” shape of the bump that increases the risk of shorting and also because of the problem of electromigration which is particularly serious at higher I/O densities.  Under these circumstances, to achieve the best performance, a copper column bump is needed.

CSR: Can you explain some more about the advantages of the copper column bump technology?

Pendse: The biggest advantage of copper column bumps is that they enable a higher I/O density with a much finer pitch between the columns than standard solder bumps along with a higher resistance to electromigration.  However, copper can be damaging to low-k dielectrics and next-generation extreme low-k (ELK) dielectrics are even more prone to this problem.  This is one of the reasons that copper hasn't been readily adopted yet. STATS ChipPAC has developed a proprietary structure that resolves this problem while allowing a high density escape routing to address high I/O density.

CSR: How is wafer bumping used for eWLB?

Pendse: eWLB is essentially a fan-out Wafer level Package.  For this package we use plating operations similar to what are used in traditional bumping only thinner to create signal lines. As for the bumps used to form the terminals of the package, we use the ball drop process (distinct from either plating or printing) in where preformed solder balls are dropped on the wafer and reflowed. This is a cost-effective process commonly used for WLCSP products as well as ball grid array packages.

CSR: How has the recent expansion of STATS ChipPAC's 300mm facility affected the company's wafer bumping operation?

Pendse: The expansion of our wafer level manufacturing hasn't significantly changed or affected our bumping operation. On the other hand, it allows us to leverage existing equipment and capacity more efficiently. We can also leverage knowhow across both bumping and wafer level manufacturing because key technologies are located in the same facility in Taiwan. We've added some tools to support our wafer level packaging operation while other tools have high capacity and can be shared.

CSR: Are there plans for more expansion to 300mm at other STATS ChipPAC locations?

Pendse: As most large foundries are in Taiwan, it is logical from a technology, logistics and cost standpoint to have the 300mm bump facility there. This provides an advantage over having the foundry located in Taiwan, but the bumping operation in China, for example. There's a strong correlation between foundry and bumping processes which enables you to manage yields better.  In the future if the foundry business grows in China, it would make sense to expand from 200mm to 300mm there. As for eWLB, this is a different process which uses wafer re-constitution, hence the size of the re-constituted wafer does not bear the same linkage to the wafer foundry as in the case of traditional bumping which is performed on the original silicon wafer. Hence our 300 mm capability for eWLB was put in Singapore without the requirement of foundry proximity.

Overall, we see significant growth going forward because of all the different products that will require TSV processes. They're all unique and different, yet have some things in common.